The filter switching-over type phase shifter is usually made up by a high-pass filter (HPF) for producing the phase lead of the signal phase, a low-pass filter for producing the phase lag of the signal phase (LPF), and single pole double throw switches (SPDT switches) for switching-over between the high-pass and low-pass filter units. The amount of phase shift is created by the phase difference produced on switching-over between these two types of the filter units.
The configuration of this filter switching-over type phase shifter will now be described. FIG. 9 is a circuit diagram showing a basic configuration of a filter switching-over type phase shifter of a type described in Patent Document 1. A high-pass filter (HPF) 112 is made up by two capacitors C111 and C112, connected in series with a signal line, and an inductor L111, connected from a junction of the two capacitors C111 and C112 to the ground. A low-pass filter (LPF) 113 is made up by two inductors L112 and L113, connected in series with a signal line, and a capacitor C113, connected from the junction of the two inductors L112 and L113 to the ground. The high-pass filter 112 and the low-pass filter 113 are connected via a single pole double throw switch (SPDTSW) 110 to an input terminal IN, while being connected via a single pole double throw switch (SPDTSW) 110 to an output terminal OUT.
The operation of the phase shifter, constructed as described above, will now be explained. If, when a signal from the input terminal IN to the output terminal OUT is passed through the high-pass filter 112, a bias, not shown, operating for turning an FET (field-effect transistor) Q101 on, is applied to the gates of FETs (field-effect transistors) Q101 and Q103, the source-drain resistance is lowered to establish a practically short-circuited state, and hence the signal is allowed to pass through the high-pass filter 112.
Meanwhile, a bias voltage, not shown, which turns off the FET, is applied to the gates of FETs Q105 and Q107, in order to inhibit the signal flowing to the low-pass filter 113, thereby increasing the source-drain resistance of the FETs Q105 and Q107.
On the other hand, when the low-pass filter 113 is turned on, the signal is allowed to flow to the low-pass filter 113 by applying the bias which is the reverse of that described above to the gates of the FETs of the single pole double throw switches 110 and 111.
In this manner, the single pole double throw switches 110 and 111 are changed (switched) over so that signals will flow through the high-pass filter 112 or the low-pass filter 113. The input signal will be delayed by the inductors L112 and L113, connected in series with the low-pass filter 113, when the signal is passed through the low-pass filter 113, while the input signal will lead (advance) by the capacitors Cl11 and C112, connected in series with the high-pass filter 112. Hence, the phase difference of the signal is produced by changing over the filter units by the single pole double throw switches 110 and 111. It is noted that, for realizing a desired phase shift value, the values of the components in the respective filter units need to be changed to optimum values.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2006-19823A (FIG. 3)